1. Field of the Disclosure
The invention relates to a multi-core processor system and a power management method thereof, and more particularly, to a multi-core processor system, a dynamic power management method thereof and a control apparatus thereof.
2. Description of Related Art
Generally, a multi-core processor system consists of a general type of processor and one or more processors having specific computing capability. The multi-core processor system adopts a concept of resource sharing to reduce the cost of hardware configuration. Therein, the resource that is most commonly shared is storage. The storage can be used for storing any type of data, including signals for indicating the communication statuses between the processors and the data simultaneously operated by multiple processors.
Recently, mobile devices, such as smart phones and tablet computers, have been rapidly popularized and gradually accepted as essentials in people's daily life. These types of devices provide a variety of functions assisting people in dealing with chores in daily life. Along with the increase on the types and amount of events to be dealt with, demands on the computing capability of the processors are also increased. If computing properties of multiple processors can be integrated in these types of device, these types of devices not only can achieve a better performance, but also can be more efficient than using single high-speed processor.
However, these types of devices usually adopt the processors using an advanced RISC machine (ARM) structure. Such a structure can not integrate multiple system function modules to provide advanced functions as x86 systems do. Taking power management for example, the system solutions that can be adopted by a processor of a non-x86 system is quite limited. Under such structure, many system function modules can not communicate with each other and therefore can not be integrated with each other to achieve advanced power management. In addition, the processor under such structure can not enter a low power state to save power consumption during a runtime stage.